The present invention relates generally to phase-locked loop (PLL) circuits, and more particularly, to methods and systems for generating a correction current in a PLL circuit.
Phase-frequency detectors (PFDs) are commonly used in phase-locked loop (PLL) circuits. PLL's are often used as part of input/output (I/O) portions microprocessors and in clock signal generating circuits. FIG. 1 is a schematic diagram of a typical PLL circuit 100 used in frequency synthesis. The PLL includes a phase-frequency detector (PFD) 102, a charge-pump 104, a loop filter 106, a voltage-controlled oscillator (VCO) 108 and a frequency divider 110. The function of each of these components is described as follows.
The PFD 102 detects a phase difference between the edges of a reference clock 122 and a second signal (e.g., a feedback clock) 124. The phase difference can be caused by a phase skew between signals of the same frequency or, a difference in frequency between the signals or a combination of both effects. The PFD 102 produces two output signals: a pump-up signal 132 and a pump-down signal 134. The width of the pump-up signal 132 and pump-down signal 134 is proportional to a detected phase difference between the reference clock 122 and the feedback clock 124. A PFD 102 can also be used in any other circuit where the phases of two signals are compared to produce one or more output signals proportional to the phase difference of the input signals.
The charge-pump 104 responds to the pump-up signal 132 and pump-down signal 134 output by the PFD 102 to deliver a net amount of charge to the loop filter 106 proportional to the phase difference between the reference clock 122 and the feedback clock 124. The pump-up signal 132 causes the charge pump 104 to source more current to the loop filter 106. The pump-down signal 134 causes the charge pump 104 to sink current from the loop filter 106. Charge-pump circuits 104 are typically used in PLL, delay-locked loop (DLL) and clock-and-data recovery (DRC) circuits among others. The PLL circuit 100 performs various task such as clock synthesis, frequency multiplication, clock deskewing, time-jitter filtering, clock-and-data recovery, etc. By way of example, the typical PLL circuit 100 can be used as part of a SERDES or other I/O's of a microprocessors as the interface between core and the external world.
The loop filter 106 converts the current 136 delivered by the charge-pump 104 into a loop filter voltage 142. The loop filter voltage 142 is then applied to the VCO 108 to adjust or tune the frequency of the VCO clock output signal 152. The VCO 108 varies its frequency of oscillation in response to the loop filter voltage 142. The VCO 108 typically uses a transfer function in Hertz/Volt to produce a VCO clock output signal 152 with a frequency corresponding to the loop filter voltage 142.
The frequency divider 110 divides the frequency of VCO clock output signal 152 by a selected division ratio (N). The resulting frequency of the signal 124 output by the frequency divider 110 is 1/N of the frequency of the VCO output signal 152. If the PLL 100 is locked on a selected frequency of the VCO clock output signal 152, the frequency of feedback clock 124 is equal to that of the reference clock 122. The phase of the feedback clock 124 is also coincidental with the phase of the reference clock 122. It can also be said that the PLL 100 multiplies the frequency of the reference clock 122 by a factor of N.
The typical PLL circuit 100 is unnecessarily complex and inefficient. As a result the performance is limited. Specifically the PFD 102 and charge pump 104 can be significantly simplified to more efficiently generate a correction current for the VCO 108.